Capacitors are widely used in many integrated circuit semiconductor devices. For example, capacitors are used to store data in Dynamic Random Access Memory (DRAM) devices. As is well known to those having skill in the art, an integrated circuit capacitor includes a first, lower or bottom electrode, a second, top or upper electrode, and a dielectric layer therebetween.
As semiconductor devices become more highly integrated, the cell size of a DRAM may decrease along with the effective area of a lower electrode of a cell capacitor. However, a predetermined amount of cell capacitance may be desirable. In order to obtain desired cell capacitance in a narrow area, a high dielectric layer formed of a material, such as Al2O3 and Al2O3/HfO2, having a dielectric constant several to several hundred times greater than a dielectric constant of an oxide/nitride/oxide (ONO) layer, may be used as a capacitor dielectric layer.
It is known to use doped polysilicon as the upper and/or lower electrodes. However, a doped polysilicon electrode used as upper and/or lower electrodes of a capacitor may react with a high dielectric layer and may deteriorate the electrical performance of the capacitor. In order to potentially solve this problem, a low dielectric layer, such as an SiON layer, may be provided between the doped polysilicon electrode and the high dielectric layer. However, the low dielectric layer may cause an increase in the overall thickness of the dielectric layer.
It is also known to use a metallic layer having a lower reactivity level than a polysilicon layer for an upper electrode of a capacitor using a high dielectric layer or for both the upper and lower electrodes of the capacitor. The metallic layer may include a layer formed of conductive oxide or conductive nitride of a metallic material as well as a layer formed of the metallic material. Thus, in addition to a semiconductor-insulator-semiconductor (SIS) capacitor using a doped polysilicon electrode as upper and/or lower electrodes, it is known to provide a metal-insulator-semiconductor (MIS) capacitor and a metal-insulator-metal (MIM) capacitor.
However, problems may occur when wet etching or dry etching an upper electrode formed of a metallic layer. Moreover, due to low resistivity, the upper electrode may not be suitable as a resistor layer for signal delay. As such, it is known to provide a double layer, formed by stacking a doped polysilicon layer on a metallic layer, for the upper electrode. Here, amorphous silicon is deposited on the metallic layer using low pressure chemical vapor deposition (LP CVD) and activation thermal treatment is performed, thereby forming the doped polysilicon layer. Unfortunately, due to the thermal treatment, the leakage current of the upper electrode formed of the double layer may be lower in comparison to the leakage current of the upper electrode formed of only the metallic layer.
FIG. 1 is a graph of voltage versus leakage current showing an increase in leakage current caused by activation thermal treatment performed on a doped polysilicon layer of a conventional MIS capacitor. Graph (a) of FIG. 1 shows the leakage current of an MIS capacitor in which only a TiN layer is used as an upper electrode and which does not use thermal treatment. Graph (b) of FIG. 1 shows the leakage current of an MIS capacitor in which a double layer formed by stacking an n-type doped polysilicon layer on a TiN layer is used as an upper electrode. In graph (b) of FIG. 1, the n-type doped polysilicon layer is deposited on the TiN layer at a temperature of 530° C. using LP CVD, and thermal treatment is performed on the n-type doped polysilicon layer in an N2 atmospheric furnace at a temperature of 600° C. for 30 minutes.
Leakage current is increased, and Tox is thicker in (b) of FIG. 1 in which activation thermal treatment is performed. Thus, it may be desirable to provide a process with a low thermal budget which can replace conventional thermal treatment conditions (such as furnace process conditions of 600° C., 30 minutes or 650° C., 2 minutes) of the n-type doped polysilicon layer.